PANEL LEVEL PACKAGING - SUPPLY CHAIN AND STRATEGIES

What is happening in the Panel Level Packaging (PLP) industry?

Extracted from: Status of Panel Level Packaging report , Yole Développement - April 2018 - NXP SCM-I.MX6 Quad High Density Fan-Out Wafer-Level System-In-Package report, System Plus Consulting, 2017.

OUTLINES:

  • PLP players are ready for high volume production.
  • Why is the industry interested in PLP?
  • What is the status of the supply chain and readiness?
  • Technical challenges and high volume manufacturing roadmap for PLP.

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LYON, France – April 26, 2018: The demand for lower cost plus higher performance, coupled with OSAT /assembly house end-customers’ desire for increasingly lower prices, has driven the semiconductor industry to develop innovative solutions. One approach to reducing overall cost is to move to a larger-size panel format. This technology, named Panel Level Packaging (PLP) takes advantage of efficiency and economies of scale.
In this favorable context, the market research and strategy consulting company Yole Développement (Yole), announces a US$285 million market in 2023, showing a 51% CAGR during the 2017-2023 period.
Detailed technology & market analysis focused on the PLP technology and market is today available in the latest advanced packaging report from Yole: Status of Panel Level Packaging 2018. This report is an update of a 2015 edition. During three years, Yole’s analysts pursue their investigation to identify the related issues and understand the evolution of this market. Why does the industry need PLP solutions today? What are the technology challenges? What the status of the development?... Yole’s team proposes today a comprehensive study including a detailed description of the current solutions per player with technical and market data as well as the analysis of PLP business opportunities.
“At Yole, we identify a sustained interest in the industry towards PLP solutions since 2015, to avail cost reductions,” explains Santosh Kumar, Senior Technology & Market Research Analyst at Yole. “This approach has clearly the ability to change the advanced packaging landscape. This is why lot of leading companies, especially equipment and material suppliers, have entered this business. Today, players are closely watching the PLP developments to explore opportunities and position themselves strategically to increase its competitive advantage.”

Many packaging platforms can be considered panel-based. Under Yole’s report, two major packaging technologies have been considered to be PLP, where both RDL interconnect fabrication and further assembly are done at panel level. They are: FOPLP and embedded die.
Between the two, FOPLP is the one which attracts the greatest interest of many players, including equipment manufacturers and suppliers, and thus is the main focus of this report.

“At Yole, we identify a sustained interest in the industry towards PLP solutions since 2015...”  (Santosh Kumar, Senior Technology & Market Research Analyst from Yole)

Lot of players have been developing FOPLP technology, but after years of development, qualification and sampling, three players will finally enter in production in 2018, announces Yole in its new PLP report: PTI – NEPES - SEMCO. NEPES has been in low-volume production since 2017. ASE, in partnership with Deca Technologies, is in the advanced development stage and will commence volume production in 2019/2020.
Each player has its own business strategy and is working on its own FOPLP technology including panel size, leveraging different infrastructure, etc... For example:
•  For example, NEPES is focused on the coarse design (>10/10 L/S), targeting automotive, sensors, and IoT applications. The company will likely not explore high-density design. NEPES’s high density FOWLP activities have been disclosed by System Plus Consulting in its reverse engineering & costing report focused on the first ultra-small multi-die low power module released by NXP: NXP SCM-i.MX6 Quad High Density Fan-Out Wafer-Level System-in-Package. “The system uses non-conventional wafer-level packaging developed by NEPES”, details Dr. Stephane Elisabeth, Project Manager, RF and Advanced Packaging, System Plus Consulting. “It has innovative interconnections, enabling a PoP configuration with Micron’s SDRAM memory chip. A custom redistribution device, called Via Frame, allows memory stacking. These components are integrated in EMC on few RDL…” (Full press release).
•  On the other hand, PTI and SEMCO’s long-term aim is to target mid and high-end applications that require 8/8 or less L/S. 
•  Meanwhile, Unimicron is working on a business model whereby it will manufacture the high-density RDL, with further assembly done by an OSAT partner or customer. 
Also, prominent OSATs like Amkor and JCET/STATS ChipPAC are currently in a “wait and see” stage, evaluating various options. They will not enter volume production before 2022.

Equipment availability for PLP is not a bottleneck today. Tools are available in the market to support various process steps in panel processing. However, certain tools that support high-density panel packaging are special and expensive. So, tool cost, not availability, is the bottleneck. For some panel-producing process steps including plating, PVD , molding, die attach, and dicing, tools are readily available and can be adapted from the PCB , flat-panel display, or LCD industries.

However, for other key process steps inherent to advanced packaging (i.e. lithography), the development of new, upgraded tool capabilities is necessary to support such steps as fine L/S patterning on panel, thick-resist lithography, panel handling capabilities, exposure field size, and depth of focus. Over the last few years, these tools have been in development at equipment suppliers. Equipment suppliers are adopting different strategies for entering the PLP business: 
•  Acquisition: for example, Rudolph Technologies has developed PLP-focused tools based on knowledge received through its acquisition of AZORES Flat Panel Display Panel Printer, in December 2012. 
•  By leveraging tool experience from other businesses and upgrading it. Yole’s analysts identified several companies such as, Evatec, Atotech and SCREEN, that selected this strategy. 
•  By organically developing PLP tools from scratch: ASM adopted this strategy. Also, some tool suppliers have a strong position in the FOWLP market. However they are skeptical of the PLP business and thus are taking a wait-and-see approach. Ultratech, Applied Materials, Lam Research are part of this group of companies.
A detailed description of this technology & market report is now available on i-micronews.com, advanced packaging reports section.

The advanced packaging team from Yole is following all year long technology innovations and market evolution. Key results and business trends are presenting during key international conferences and trade shows. Next date will be at MINAPAD taking place in Grenoble, on May 16&17. During the conference, Emilie Jolivet, Division Director, Semiconductor & Computing at Yole, proposes a presentation titled: “High End Performance Application key Driver for Advanced Packaging” (May 16 at 2:15 PM). Do not hesitate to meet the team on booth 6.

In addition to its participation to ECTC 2018 (From May 29 to June 1 – Booth #404 in San Diego, CA, USA), Yole is also organizing its own advanced packaging event, “Advanced Packaging & System Integration Technology Symposium” on June 20&21, 2018 in Wuxi, China. During the 2-day symposium, the market research and strategy consulting company, with its partner NCAP, invite you to discover a valuable program focused on panel Level, Fan Out, System in Package, Advanced Substrates, 3D Technology will be discussed. Focus on key applications such as 5G, Automotive, Artificial Intelligence and Memory will be at the heart of the conference…
Full program, registration & sponsorship opportunities on i-micronews.com – Contact: Camille Veyrier (Veyrier@yole.fr).

Acronyms:
OSAT : Outsourced Semiconductor Assembly and Test
PLP : Panel Level Packaging
RDL : Redistribution Layer
FOPLP : Fan-Out Panel Level Packaging
PTI : Powertech Technologies
FOWLP: Fan-Out Wafer Level Packaging
PVD : Physical Vapor Deposition
PCB : Printed Circuit Board
LCD : Liquid Crystal Display
ASM : ASM Pacific Technology Limited




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